48LC8M16A2 Datasheet – 2 Meg x 16 x 4 Banks SDR SDRAM

The Microchip Technology Inc. 48L256 serial EERAM has an SRAM memory core with hidden EEPROM backup. The device can be treated by the user as a full symmetrical read/write SRAM. Backup to EEPROM is handled by the device on any power disrupt, so the user can effectively view this device as an SRAM that never loses its data.

The device is structured as a 256-Kbit SRAM with EEPROM backup in each memory cell. The SRAM is organized as 32,768 x 8 bits and uses the SPI serial interface. The SPI bus uses three signal lines for communication: clock input (SCK), data in (SI), and data out (SO). Access to the device is controlled through a Chip Select (CS) input, allowing any number of devices to share the same bus. The SRAM is a conventional serial SRAM: it allows symmetrical reads and writes and has no limits on cell usage. The backup EEPROM is invisible to the user and cannot be accessed by the user independently. The device includes circuitry that detects VCC dropping below a certain threshold, shuts its connection to the outside environment, and transfers all SRAM data to the EEPROM portion of each cell for safe keeping. When VCC returns, the circuitry automatically returns the data to the SRAM and the user’s interaction with the SRAM can continue with the same data set.

Part Number	48LC8M16A2, MT48LC8M16A2
Function	2 Meg x 16 x 4 Banks SDR SDRAM
Package
Manufacturer	Micron Technology
Datasheet	Download PDF

48LC8M16A2 NO Features

• Serial SRAM Features
  • Unlimited Reads/Unlimited Writes:
  • SRAM Array:
  • High-Speed SPI Interface:
  • Low-Power CMOS Technology:
• Hidden EEPROM Backup Features
  • Cell-Based Nonvolatile Backup:
  • Invisible-to-User Data Transfers:
• Other Features of the 48L256
  • Temperature Ranges:
• Packages

48LC8M16A2 Datasheet