74LS76 Dual JK Flip-Flop with Preset and Clear
Package CDIP Series 74LS
74LS76 overview
The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. The 74LS76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs.
The 74LS76 is a positive-edge-triggered flip-flop. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices, the J and K inputs must be stable while the clock is high.
Key specifications
Supply Voltage
4.75 - 5.25Vdc
Maximum Clock Frequency
40Mhz
Power Dissipation
2mW/gate @100kHz
Minimum Output Current
8mA
Propagation Delay
10nS
Fan Out (TTL Loads)
20
Datasheet
sn54ls76a.pdf
74LS76 features
- Two Individual Flip-Flops with J,K Clock, Set and Clear Inputs
- Input Data is Transferred to the Outputs on HIGH-LOW Clock Transition
- Fast Switching Speed
- Operating Temperature up to 70°C
- Standard TTL Switching Voltages
74LS76 pinout
| Pin | Name | Description |
|---|---|---|
| 1 | CLK 1 | Clock Pin 1 |
| 2 | PRE' 1 | Invert Preset Pin 1 |
| 3 | CLR' 1 | Invert Clear Pin 1 |
| 4 | J1 | Data Input J1 |
| 5 | VCC | Supply Voltage |
| 6 | CLK 2 | Clock Pin 2 |
| 7 | PRE' 2 | Invert Preset Pin 2 |
| 8 | CLR' 2 | Invert Clear Pin 2 |
| 9 | J2 | Data Input J2 |
| 10 | 2Q' | Invert Output Pin 2Q' |
| 11 | 2Q | Output Pin 2Q |
| 12 | 2K | Data Input 2K |
| 13 | GND | Ground Pin |
| 14 | 1Q' | Invert Output Pin 1Q' |
| 15 | 1Q | Output Pin 1Q |
| 16 | 1K | Data Input 1K |
74LS76 applications
- Event Detectors
- Data Synchronizers
- Frequency Divider
Application circuit
More about 74LS76
74LS76 Circuit
Here is a simple circuit of J-K Flip Flop with Clock Pin using Logic Gate NAND.
74LS76 Alternative Equivalent
74LS73, 74LS107
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