ATMEGA128-16AU Datasheet – 8-bit Microcontroller IC
8-bit Microcontroller with 128K Bytes In-System Programmable Flash
Package 64-lead TQFP Series ATmega (AVR)
ATMEGA128-16AU overview
The Atmel® AVR® core combines a rich instruction set with 32 general-purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega128 device is supported with a full suite of program and system development tools including C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits
| Part Number | ATMEGA128-16AU |
| Function | 8-bit Microcontroller with 128K Bytes In-System Programmable Flash |
| Package | 64-lead TQFP |
| Manufacturer | ATMEL Corporation |
| Datasheet | Download PDF  |
Datasheet
atm-ega128-datasheet.pdf
ATMEGA128-16AU features
- High-performance, Low-power Atmel®AVR®8-bit Microcontroller
- Advanced RISC Architecture
- 133 Powerful Instructions – Most Single Clock Cycle Execution
- 32 x 8 General Purpose Working Registers + Peripheral Control Registers
- Fully Static Operation
- Up to 16MIPS Throughput at 16MHz
- On-chip 2-cycle Multiplier
- High Endurance Non-volatile Memory Segments
- 128Kbytes of In-System Self-programmable Flash program memory
- 4Kbytes EEPROM
- 4Kbytes Internal SRAM
- Write/Erase cycles: 10,000 Flash/100,000 EEPROM
- Data retention: 20 years at 85°C/100 years at 25°C(1)
- Optional Boot Code Section with Independent Lock Bits
- In-System Programming by On-chip Boot Program
- True Read-While-Write Operation
- Up to 64Kbytes Optional External Memory Space
- Programming Lock for Software Security
- SPI Interface for In-System Programming
- QTouch® library support
- Capacitive touch buttons, sliders, and wheels
- QTouch and QMatrix acquisition
- Up to 64 sense channels
- JTAG (IEEE std. 1149.1 Compliant) Interface
- Boundary-scan Capabilities According to the JTAG Standard
- Extensive On-chip Debug Support
- Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
- Peripheral Features
- Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
- Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode
- Real-Time Counter with Separate Oscillator
- Two 8-bit PWM Channels
- 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
- Output Compare Modulator
- 8-channel, 10-bit ADC
- 8 Single-ended Channels
- 7 Differential Channels2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
- Byte-oriented Two-wire Serial Interface
- Dual Programmable Serial USARTs
- Master/Slave SPI Serial Interface
ATMEGA128-16AU pinout
| Name | Description |
|---|---|
| VCC | Digital supply voltage |
| GND | Ground |
| Port A (PA7..PA0) | Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up res |
| Port B (PB7..PB0) | Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up res |
| Port C (PC7..PC0) | Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up res |
| Port D (PD7..PD0) | Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up res |
| Port E (PE7..PE0) | Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up res |
| Port F (PF7..PF0) | Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resi |
| Port G (PG4..PG0) | AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter |
| Reset | Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. |
| XTAL1 | Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. |
| XTAL2 | Output from the inverting Oscillator amplifier. |
| AVCC | PEN is a programming enable pin for the SPI Serial Programming mode and is internally pulled high. By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has no function during normal operation. |
| AREF | AREF is the analog reference pin for the A/D Converter |
| PEN | PEN is a programming enable pin for the SPI Serial Programming mode and is internally pulled high. By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Pro- gramming mode. PEN has no function during normal operation. |
ATMEGA128-16AU applications
- One USART instead of two, Asynchronous mode only. Only the eight least significant bits of
- One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters
- Two-wire serial interface is not supported.
- Port C is output only.
- Port G serves alternate functions only (not a general I/O port).
- Port F serves as digital input only in addition to analog input to the ADC.
- Boot Loader capabilities is not supported.
- It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
- The External Memory Interface can not release any Address pins for general I/O, neither
- Only EXTRF and PORF exists in MCUCSR.
- Timed sequence not required for Watchdog Time-out change.
- External Interrupt pins 3 - 0 serve as level interrupt only.
- USART has no FIFO buffer, so data overrun comes earlier.
More about ATMEGA128-16AU
ATMEGA128-16AU Features
- Advanced RISC Architecture
- High Endurance Non-volatile Memory Segments
- Optional Boot Code Section with Independent Lock Bits
- QTouch® library support
- JTAG (IEEE std. 1149.1 Compliant) Interface
- Peripheral Features
- 8-channel, 10-bit ADC
- Programmable Watchdog Timer with On-chip Oscillator
- On-chip Analog Comparator
- Special Microcontroller Features
- Power-on Reset and Programmable Brown-out Detection
- External and Internal Interrupt Sources
- Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
- Software Selectable Clock Frequency
- ATmega103 Compatibility Mode Selected by a Fuse
- Global Pull-up Disable
- I/O and Packages
- 53 Programmable I/O Lines
- 64-lead TQFP and 64-pad QFN/MLF
- Operating Voltages
- 2.7 - 5.5V ATmega128L
- 4.5 - 5.5V ATmega128
- Speed Grades
- 0 - 8MHz ATmega128L
- 0 - 16MHz ATmega128
Pin Definitions
| Pin Name | Description |
|---|---|
| Port A (PA7..PA0) | Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. |
| Port B (PB7..PB0) | Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. |
| Port C (PC7..PC0) | Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. |
| Port D (PD7..PD0) | Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. |
| Port E (PE7..PE0) | Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. |
| Port F (PF7..PF0) | Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. In ATmega103 compatibility mode, these pins only serve as strobes signals to the external memory as well as input to the 32kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are oscillator pins. |
Comments 0
Leave a comment