74LS125 Quad Bus Buffer Negative Enable Tri-State
Package PDIP, SOIC Series 74LS
74LS125 overview
The 74LS series of integrated circuits (ICs) was one of the most popular logic families of transistor-transistor logic (TTL) logic chips. 74LS series is a bipolar, low-power Schottky IC. 74LS125 bus buffers feature three-state outputs that, when enabled, have the low impedance characteristics of a TTL output with additional drive capability at high logic levels to permit driving heavily loaded bus lines without external pullup resistors.
Key specifications
Supply Voltage
4.75 - 5.25Vdc
Maximum Clock Frequency
40Mhz
Power Dissipation
2mW/gate @100kHz
Minimum Output Current
8mA
Propagation Delay
10nS
Fan Out (TTL Loads)
20
Datasheet
125.pdf
74LS125 features
- Four Independent Non-Inverting Buffer Gates
- Enabled Mode
- Fast Switching Times
- Operating Temperature up to 70°C
- Standard TTL Switching Voltages
74LS125 pinout
| Pin | Name | Description |
|---|---|---|
| 1 | E' | Invert Enable Pin Of Buffer 1 |
| 2 | D | Data Input Of Buffer 1 |
| 3 | O | Output Of Buffer 1 |
| 4 | E' | Invert Enable Pin Of Buffer 2 |
| 5 | D | Data Input Of Buffer 2 |
| 6 | O | Output Of Buffer 2 |
| 7 | GND | Ground |
| 8 | O | Output Of Buffer 3 |
| 9 | D | Data Input Of Buffer 3 |
| 10 | E' | Invert Enable Pin Of Buffer 3 |
| 11 | O | Output Of Buffer 4 |
| 12 | D | Data Input Of Buffer 4 |
| 13 | E' | Invert Enable Pin Of Buffer 4 |
| 14 | VCC | Positive Supply |
74LS125 applications
- A buffer or a voltage buffer is used to isolate input from the output. The buffer's output state mirrors the input state.
More about 74LS125
74LS125 Alternative Equivalent
74LS126
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